Semiconductor device and method for manufacturing same

ABSTRACT

An object of the present invention is to mount both a RF circuit including an inductor formed therein and a digital circuit on a single chip. 
     MOSFETs are formed on a semiconductor substrate  1  in regions isolated by an element isolation film  2 . A plurality of low-permittivity insulator rods including a low-permittivity insulator embedded therein and penetrating a first interlevel dielectric film  4  to reach the internal of the silicon substrate are disposed in the RF circuit area  100 . An inductor  40  is formed on the interlevel dielectric film in the RF circuit area by using multi-layered interconnects. A high-permeability isolation region in which a composite material including a mixture of high-permeability material and a low-permittivity material is formed in the region of the core of the inductor and periphery thereof.

This application claims the benefit of International Patent ApplicationNo. PCT/JP2004/008450, filed Jun. 16, 2004, which claims priority ofJapanese patent application No. 2003-170267.

TECHNICAL FIELD

The present invention relates to a semiconductor device capable ofprocessing a high-frequency signal and a fabrication method thereof and,more particularly, to a semiconductor device including at least ahigh-frequency signal processing area on a semiconductor substrate and afabrication method thereof.

BACKGROUND ART

Development of mobile computing requires a silicon chip to have a radiofrequency communication function (RF communication function). Aconventional silicon chip has therein CMOS gates including CMOStransistors, wherein signal processing is performed only in a digitallogic processing scheme using the CMOS gates. On the other hand, the RFcommunication function is directed to analog signal processing, andincludes an amplifying function for a received wave by using passiveelements such as inductors, and a transmitting function using pulsegenerator, pulse delay circuit etc., in addition to an analog processingfunction of the CMOS transistors, such as an analog signal amplificationfunction.

More specifically, a communication terminal includes in a siliconsemiconductor chip, as shown in FIG. 26, at least a RF communicationcircuit area 61 including a LNA (Low noise amplifier) 61 a, atransmission signal generating circuit 61 b and a switch circuit 61 c,and a digital baseband (BB) area 62 including an A/D converter 62 a forconverting those analog signals into digital signals, a digital signalprocessing circuit 62 b, and a D/A converter for again converting thedigital signals, for which signal processing is performed, into analogsignals. Although a memory area such as SRAM and DRAM is needed thereinin fact, it is not depicted in the figure.

The amplifying function of the CMOS transistors is significantlyimproved along with the development of the micro-fabrication technique,to the extent that enables the analog signal processing in the RF area.However, the analog circuit requires an LCR circuit configuration, andthere are technical problems in development of the high-performance andsmall-size inductors formed on the silicon semiconductor chips, wherebythe practical application thereof is delayed. FIG. 27 shows a schematictop plan view of an inductor formed on a silicon semiconductor chip andan equivalent circuit thereof. The inductor is formed by usingmulti-layered interconnects formed on the silicon semiconductor chip.

If the loss of the inductor is neglected, the inductance L of theinductor is expressed by the following formula (1):L∝μ×n2×r  (1),where μ, n and r are permeability of the inductor-formed area, number ofwindings and a maximum radius of the windings, respectively.

A silicon oxide film is used for the isolation between the multi-layeredinterconnects, and the permittivity can be assumed as the permittivityμ₀ of vacuum. According to the formula (1), it is necessary to adoptn=26 as the number of windings and around 2r=250 μm as one side of theinductor, for obtaining L=100 nH. Although this is an extremely smallsize compared to the off-chip inductor part, it occupies a large area inthe normal logic chip. Thus, it is difficult to use a large number ofinductors in the RF circuit. Increase of the inductance L withoutchanging the size of the inductor can be achieved by raising thepermeability of the inductor-formed area. The formula (1) shows this isachieved by adopting a high-permeability material.

In the formula (1), the inductance (L) of the inductor is noticed. Theinductor has a power loss factor, as shown by the equivalent circuit onthe silicon semiconductor chip in FIG. 27, which impedes thehigh-frequency characteristic of the circuit. For example, theresistance (Rs) of the inductor line configured by the multi-layeredinterconnects causes a large power dissipation because a large-sizeinductor has an increased line length. In addition, the loss bycharge/discharge of the coupling capacitance (Cp) between the lines ofthe inductor, the loss by the coupling capacitance (Cox/2) between theinductor and the silicon semiconductor substrate, and the loss caused bythe p-n junction capacitance in the silicon substrate are the causes ofthe large power dissipation.

As another factor other than the above losses, there is a noisepropagation via the silicon substrate and the loss thereof, which isincurred by an induction current (eddy current) due to the fluctuationof the high-frequency magnetic field from the inductor. The noisepropagation phenomenon is a technical problem common to the RF circuitsformed on the silicon semiconductor substrate as well as the inductor.For reducing the substrate noise, it is important to increase thesubstrate resistance (R1) and reduce the substrate capacitance (C1). Itis to be noted that the substrate resistance R1 is determined by thespecific resistance ρ and the substrate thickness t_(sub).

Under the technical background as described above, the technicaldevelopment for forming a high-performance inductor on the siliconsemiconductor substrate has been advanced. A first conventionaltechnique is such that a groove (trench) is formed on a siliconsubstrate in an inductor-forming area and filled with a silicon oxideetc. (refer to, for example, JP-A-2000-77610, 2002-93622 and2000-40789).

FIG. 28 is a sectional view of the on-chip inductor proposed inJP-A-2000-77610. As shown in the same figure, lattice-like trenches areformed on a silicon substrate 71 and filled with a silicon oxide film72, and an inductor 73 is formed on the resultant trench-forming area.Embedding the silicon oxide film 72 within the silicon substrate 71reduces the capacitance (C1) of the inductor-formed area and thecoupling capacitance (Cox/2) between the inductor line and thesubstrate, thereby achieving reduction of the leakage current andinductive current of the inductor.

JP-A-2002-93622 describes an element wherein a spiral trench is formedon a silicon substrate in the gaps between spiral lines of the inductorand the outer periphery thereof, and the trench is filled with aninsulating material (silicon oxide).

JP-A-2000-40789 describes a technique wherein an inductor is formedusing multi-layered interconnects on a silicon substrate, and an openingformed from the surface of the silicon substrate is filled with aninsulator (silicon dioxide, or silicon nitride) and an intrinsicsilicon, whereby a plate-like insulating film and a shallow-trenchinsulating film are alternately formed from the surface of the siliconsubstrate toward the internal of the substrate in the inductor-formedarea.

The techniques as described above are such that the silicon substrate isdrilled from the surface thereof and the internal of the resultantstructure is filled with an insulator.

As a second conventional technique, it is proposed to increase thepermeability of the periphery of the windings by embedding aferromagnetic or soft magnetic material within the inductor-formingarea, thereby increasing the inductance (refer to, for example,JP-A-2001-284533). More specifically, JP-A-284533 describes a techniquewherein windings of an inductor 83 are formed in an insulating film 82on a silicon substrate 81, and a magnetic core 84 made of aferromagnetic substance such as an iron-cobalt alloy is disposed in theinsulating film in the central area (and the peripheral area) of thewindings, as shown in FIG. 29.

JP-A-2001-285433 describes a technique for reducing the resistance of aninductor line by connecting together a first interconnect layer and asecond interconnect layer and thus using a plurality of interconnectlayers.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention

All the conventional techniques are proposed for improving theperformance of the inductors that are formed on the silicon substrate,and have respective problems as described hereinafter. In either of thefirst conventional techniques, the groove or trench is drilled from thesurface of the silicon substrate. In addition,relatively-high-permittivity materials such as silicon oxide and siliconnitride are to be used as the insulating materials for filling thegroove or trench are. Although it is effective to embed an insulatingfilm having a lower permittivity for reducing the parasitic capacitance,the low-permittivity insulating film cannot be used in the conventionaltechniques because a transistor-forming process is scheduled afterembedding the insulating film. As the low-permittivity insulating films,known are an organic siloxane film wherein the oxygen of silicon oxideis partially replaced by organic groups such as a methyl group, a porousinsulating film wherein a number of tiny pores having a diameter of 5 nmor less are distributed in an organic siloxane film, and so on. However,these low-permittivity insulating films in general have a heatresistance at a temperature of around 500 degrees C. or lower. On theother hand, a high-temperature heat treatment as high as at 700 degreesC. is necessary for manufacturing the transistors in the steps such asforming a gate insulating film or activation annealing after impurityimplantation. Use of a structure, wherein the insulating film isembedded in the inductor-forming area before forming the transistors,inevitably limits the embedded insulating film to a silicon oxide filmetc having a higher heat resistance. Accordingly, the first conventionaltechniques do not well reduce the parasitic capacitance with respect tothe substrate.

In addition, although an object of the first conventional techniques isto reduce the substrate current, there is no consideration as to therelationship between the trench depth and the silicon substratethickness, i.e., to what depth the trench is to be drilled in relationto the thickness of the silicon substrate. Since the silicon substrateis doped with impurities and thus has a low resistance, the substratecurrent cannot be well reduced so long as the substrate has a largethickness. That is, it is impossible to well reduce the noise and losstherein.

In the second conventional technique as described above, an openingprovided therein has a large area compared to its depth and is filledwith a ferromagnetic substance. In the case where the cross-sectionalarea/diameter of the ferromagnetic substance is larger compared to theembedded depth, there is an increased loss resulting from the eddycurrent caused by fluctuation of the magnetic field passing through theferromagnetic substance area. For reducing the eddy current, thecross-sectional area must be reduced. However, a smaller cross-sectionalarea employed alone is not expected to improve the magnetic flux densitydue to the resultant smaller covering area for the core region.

Furthermore, for reducing the loss of the inductor, it is necessary toreduce the coupling capacitance (Cp) between the lines of the inductor.JP-A-2001-284533 as described above describes embodiments wherein themagnetic core is configured by soft magnetic particles which are fixedtogether using polyimide. However, there is no consideration as to thereduction of Cp, and remains in the mere use of organic adhesive(polyimide) having a relative permittivity of 3 or above for fixing themagnetic substance.

In the same publication, JP-A-2001-284533, it is recited that theelectrical connection of two interconnect layers in parallel can reducethe resistance loss of the inductor line; however, there is a problem inthat the use of the underlying interconnect layer as an interconnect ofthe inductor increases the parasitic capacitance. That is, use of thelower-level interconnect layer that is in the closer vicinity of thesubstrate causes a smaller distance from the substrate, resulting in theproblem of an increase of the parasitic capacitance Cox between theinterconnect and the substrate in the equivalent circuit shown in FIG.27 and thus causing the problem of degradation in the performance of theinductor.

It is an object of the present invention to solve the above problems andto provide a semiconductor device which includes at least ahigh-frequency signal processing circuit area on a semiconductorsubstrate, and is capable of reducing loss and noise in thehigh-frequency range and especially reducing the size and loss of theinductor used as a passive element.

Means for Solving the Problems

In order to achieve the above object, the present invention provides, ina first aspect thereof, a semiconductor device including a semiconductorsubstrate having therein a low-capacitance substrate region, atransistor formed on a surface area of the semiconductor substrate, anda multi-layered interconnection structure including a plurality ofinterlevel dielectric films and a plurality of interconnect layersoverlying the transistor, characterized in that a plurality of substrateopenings are formed in the low-capacitance substrate region, penetratingat least an undermost one of the interlevel dielectric films to reach aninternal of the semiconductor substrate.

It is preferable that a low-permittivity insulating material be embeddedin the substrate openings. It is more preferable that a length of thesubstrate openings within the semiconductor substrate be equal to orlarger than half a thickness of the semiconductor substrate, or thesubstrate opening penetrate the semiconductor substrate.

In order to achieve the above object, the present invention provides, ina second aspect thereof, a semiconductor device including asemiconductor substrate, a transistor formed on a surface area of thesemiconductor substrate, and a multi-layered interconnection structureincluding a plurality of interlevel dielectric films and a plurality ofinterconnect layers overlying the transistor, wherein ahigh-permeability region is provided in an interlevel dielectric film,characterized in that the high-permeability region includes therein aplurality of high-permeability magnetic rods including ahigh-permeability material having an electric conductivity and embeddedin respective film openings, the film openings having an aspect ratio(depth/diameter or a side) of 1 or above and penetrating at least one ofthe interlevel dielectric films to reach another of the interleveldielectric films.

In order to achieve the above object, the present invention provides, ina third aspect thereof, semiconductor device wherein oxide-based thehigh-permeability region includes a plurality of high-permeabilitymagnetic rods including a high-permeability material having aninsulating property and embedded in respective film openings, the filmopenings penetrating at least one of the interlevel dielectric films toreach another of the interlevel dielectric films.

It is preferable that the high-permeability material be a compositematerial including a low-permittivity insulating material and ahigh-permeability material having an electric conductivity or aninsulating property. The high-permeability material having an insulatingproperty is an oxide-based high-permeability material, for example.Examples of the high-permeability material having an electricconductivity include: a NiFe-based binary alloy, and polymetal alloysincluding this binary alloy and an additive element such as Mo, Cr, Cuand Co, i.e., generally called Permalloy-based materials; Fe—Co-basedalloy, Ni—Co-based alloy, Fe—Al-based alloy, Fe—Al—Si alloy generallycalled Sendast, and these alloys added with a minute amount of otherelements; amorphous materials such as FeP-based and FeB-based alloys,and these alloys added with other elements; amorphous-state formingelement including SiB, such as FeSiB, NiSiB, CoSiB, CoFeSiB, CoFeNiSiB,CoFeMoSiB, CoFeNiNbSiB, and CoFeMnSiB; amorphous materials for aCo-based sputtered film, such as Co—(Zr, Hf, Nb, Ta, Ti)-based materialand metal-metal alloys added with several percents of Fe, Mn and Ni,such as CoFePbAl, CoMnB, CoMoZr, CoTaZr, CoNbZr, CoNbTi, CoFeNb, C0MnNb.Granular-film materials such as FeTaN and FeTaC may also be used forthis purpose.

Examples of the oxide-based high-permeability material include:materials generally called ferrite expressed by chemical formula MFe₂O₄(M represents divalent metal ions such as Mn²⁺, Ni²⁺ and Cu²⁺); andmaterials generally called composite ferrite, i.e., mixture of thoseferrite materials and non-magnetic oxide such as ZnFe₂O₄, for example,Mn—Zn ferrite, Mg—Fe ferrite, Cu—Zn ferrite, Cu—Zn—Mg ferrite, Ni—Cu—Znferrite. Moreover, Mn—Mg ferrite, Mn—Mg—Al ferrite, Ni ferrite, Ni—Znferrite and YIG(Y₂Fe₅O₁₂), which are used in relatively-high-frequencyranges such as MHz range and GHz range; garnet-type ferrite wherein YIGis added with a minute amount of additive elements, such as Al-basedYIG, Gd-based YIG, Ca-based YIG, Nb-based YIG; hexagonal-system-type Baferrite and Ba ferrite added with a minute amount of other elements; andNi—Co ferrite and Ni—Cu—Co—Fe ferrite may also be exemplified aspreferable materials.

It is to be noted that those examples of high-permeability material donot limit the present invention, and that the composition ratio as tothe recited examples of the soft magnetic material is not consideredhere, which therefore do not limit the present invention.

In order to achieve the above object, the present invention provides, ina fourth aspect thereof, a semiconductor device including asemiconductor substrate having therein a low-capacitance substrateregion, a transistor formed on a surface area of the semiconductorsubstrate, and a multi-layered interconnection structure including aplurality of interlevel dielectric films and a plurality of interconnectlayers overlying the transistor, characterized in that a plurality ofsubstrate openings are formed in the low-capacitance substrate region,penetrating at least an undermost one of the interlevel dielectric filmsto reach an internal of the semiconductor substrate, and a plurality ofinterconnect layers including at least two interconnect layers areformed overlying the low-capacitance substrate region.

In order to achieve the above object, the present invention provides, ina fifth aspect thereof, a method for manufacturing a semiconductordevice including a semiconductor substrate, a transistor formed on asurface area of the semiconductor substrate, and a multi-layeredinterconnection structure including a plurality of interlevel dielectricfilms and a plurality of interconnect layers overlying the transistor,wherein a high-permeability region is provided in the interleveldielectric film, the method including the consecutive steps of:

(1) forming the transistor on the semiconductor substrate;

(2) forming a plurality of substrate openings penetrating at leastundermost one of the interlevel dielectric films to reach an internal ofthe semiconductor substrate;

(3) embedding an insulating material in the openings; and

(4) grinding a bottom surface of the semiconductor substrate.

EFFECTS OF THE INVENTION

In a preferred embodiment of the semiconductor device of the presentinvention, low-permittivity insulator rods including low-permittivityinsulating film embedded in the semiconductor substrate underlying theinductor-forming region are disposed, and the substrate thickness ismade small. This configuration is capable of suppressing the couplingcapacitance between the inductor and the substrate to a lower value andalso reducing the current induced in the substrate.

Moreover, if the inductor-forming region is provided withhigh-permeability material rods wherein a soft magnetic material isembedded within openings having a high aspect ratio, size reduction ofthe inductor can be achieved while suppressing the eddy current.

A configuration wherein a mixture of a soft magnetic material(high-permeability material) and a low-permittivity material is embeddedwithin the openings in the inductor-forming area, if employed, achievesreduction in the capacitance between the lines of the inductor inaddition to the size reduction of the inductor. This configurationreduces the loss and size of the RF circuit including the inductor, andachieves a semiconductor chip on which both a digital signal processingfunction and a RF circuit are mounted.

In the present invention, the semiconductor substrate is not limited toany specific one. By forming an area including low-permittivityinsulator rods embedded in a silicon semiconductor substrate on whichCMOS devices are formed, the silicon substrate, which is inherently alow resistance material, is provided with a high-resistance andlow-permittivity area as a low-noise propagation area in a desiredportion of the silicon substrate. The multi-layered interconnectionstructure includes an interconnection structure including two or moreinterconnect layers.

BRIEF DESCRIPTION OF HE DRAWINGS

FIG. 1 is a sectional view of a semiconductor device according to afirst embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor device according to asecond embodiment of the present invention.

FIG. 3 is a top plan view of a first example of the arrangement ofopenings in which a low-permittivity material is embedded.

FIG. 4 is a top plan view of a second example of the arrangementopenings in which a low permittivity material is embedded.

FIG. 5 is a sectional view of a semiconductor device according to athird embodiment of the present invention.

FIG. 6 is a sectional view of a semiconductor device according to afourth embodiment of the present invention.

FIG. 7 is a block diagram exemplifying the state of use of the device onwhich a plurality of semiconductor devices according to the presentinvention are mounted.

FIG. 8 includes a top plan view and a sectional view of a semiconductordevice of a first example of the present invention.

FIG. 9 includes a top plan view and a sectional view of thesemiconductor device of the first example in a process step of afabrication method thereof.

FIG. 10 includes a top plan view and a sectional view of thesemiconductor device of the first example in a process step of afabrication method thereof.

FIG. 11 includes a top plan view and a sectional view of thesemiconductor device of the first example in a process step of afabrication method thereof.

FIG. 12 includes a top plan view and a sectional view of thesemiconductor device of the first example in a process step of afabrication method thereof.

FIG. 13 includes a top plan view and a sectional view of thesemiconductor device of the first example in a process step of afabrication method thereof.

FIG. 14 includes a top plan view and a sectional view of thesemiconductor device of the first example in a process step of afabrication method thereof.

FIG. 15 includes a top plan view and a sectional view of thesemiconductor device of the first example in a process step of afabrication method thereof.

FIG. 16 includes a top plan view and a sectional view of thesemiconductor device of the first example in a process step of afabrication method thereof.

FIG. 17 includes a top plan view and a sectional view of thesemiconductor device of the first example in a process step of afabrication method thereof.

FIG. 18 includes a top plan view and a sectional view of thesemiconductor device of the first example in a process step of afabrication method thereof.

FIG. 19 includes a top plan view and a sectional view of a semiconductordevice of a second example of the present invention.

FIG. 20 includes a top plan view and a sectional view of a semiconductordevice of a third example of the present invention.

FIG. 21 includes a top plan view and a sectional view of a semiconductordevice of a fourth example of the present invention.

FIG. 22 includes a top plan view and a sectional view of a semiconductordevice of a fifth example of the present invention.

FIG. 23 includes a top plan view and a sectional view of a semiconductordevice of a sixth example of the present invention.

FIG. 24 includes a top plan view and a sectional view of a semiconductordevice of a seventh example of the present invention.

FIG. 25 includes a top plan view and a sectional view of a semiconductordevice of an eighth example of the present invention.

FIG. 26 is a block diagram of a typical semiconductor chip including atransmission/reception function.

FIG. 27 includes a top plan view and an equivalent circuit diagram of aninductor formed on a semiconductor substrate.

FIG. 28 is a sectional view of a first conventional technique.

FIG. 29 is a sectional view of a second conventional technique.

FIG. 30 is a sectional view showing a fifth embodiment of the presentinvention.

FIG. 31 is a top plan view showing that a plurality of interconnectlayers are connected in parallel through via-plugs.

FIG. 32 is a sectional view showing a sixth embodiment of the presentinvention.

FIG. 33 is a top plan view showing that ends of a plurality ofinterconnect layers are connected electrically in series throughvia-plugs.

FIG. 34 is a top plan view showing that ends of a plurality ofinterconnect layers are connected electrically in series throughvia-plugs.

FIG. 35 includes a top plan view and a sectional view showing that endsof a plurality of interconnect layers are connected electrically inseries through via-plugs.

FIG. 36 includes a top plan view and a sectional view showing that endsof a plurality of interconnect layers are connected electrically inseries through via-plugs.

FIG. 37 includes a top plan view and a sectional view showing that endsof a plurality of interconnect layers are connected electrically inseries through via-plugs.

FIG. 38 includes a top plan view and a sectional view showing that endsof a plurality of interconnect layers are connected electrically inseries through via-plugs.

FIG. 39 is a sectional view according to a seventh embodiment of thepresent invention.

FIG. 40 is a sectional view according to an eighth seventh embodiment ofthe present invention.

FIG. 41 is a sectional view according to a ninth embodiment of thepresent invention.

FIG. 42 is a sectional view of a fabrication step for the seventhembodiment of the present invention.

FIG. 43 is a sectional view of a fabrication step for the seventhembodiment of the present invention.

FIG. 44 is a sectional view of a fabrication step for the seventhembodiment of the present invention.

FIG. 45 is a sectional view of a fabrication step for the seventhembodiment of the present invention.

FIG. 46 is a sectional view of a fabrication step for the eighthembodiment of the present invention.

FIG. 47 is a sectional view of a fabrication step for the eighthembodiment of the present invention.

FIG. 48 is a sectional view of a fabrication step for the eighthembodiment of the present invention.

FIG. 49 is a sectional view of a fabrication step for the ninthembodiment of the present invention.

FIG. 50 is a sectional view of a fabrication step for the ninthembodiment of the present invention.

FIG. 51 is a sectional view of a fabrication step for the ninthembodiment of the present invention.

FIG. 52 is a top plan view showing a third example of the arrangement ofopenings in which a low-permittivity material is embedded.

FIG. 53 is an explanatory diagram showing an embedded depth dependencyof the low-permittivity filling member having a Q-value of the inductorin the first embodiment of the present invention.

FIG. 54 is an explanatory diagram showing an embedded depth dependencyof the low-permittivity filling member having a Q-value of the inductorin the first embodiment of the present invention.

EMBODIMENTS OF THE INVENTION

Hereinafter, the present invention will be described in detail withreference to the drawings based on the embodiments of the presentinvention. Similar constituent elements will be denoted by similarreference numerals throughout the drawings.

Referring to FIG. 1, a semiconductor chip according to a firstembodiment of the present invention includes an RF circuit area 100 forprocessing high-frequency analog signals, and a digital circuit area 200for processing digital signals. On a semiconductor substrate 51 isformed a layered insulating structure including a plurality ofinterlevel dielectric films. In the layered insulating structure 52 inthe RF circuit area 100, there is provided an inductor 53 having, forexample, a spiral structure while using multi-layered interconnects. Inthe RF circuit area 100 are provided openings which penetrate at leastone interlevel dielectric film to reach the internal of thesemiconductor substrate 51. Within the openings is embedded alow-permittivity filling member 54 having a relative permittivity lowerthan that of a silicon oxide film. The openings may be a circle orpolygon such as quadrangle as viewed normal to the substrate. In analternative, the openings may have a so-called honey-comb structurewherein hexagon openings are arranged so as to obtain a higher fillingfactor. In this case, the hexagons need not be regular hexagons, and forexample, may have a shape of hexagon such as shown in FIG. 52, wherein apair of opposing angles are each 90 degrees. The shape of hexagon shownin FIG. 52 is based on the restriction of a semiconductor device design,wherein the angle of an allowable line in the design is limited to 0, 45or 90 degrees with respect to a reference line. Since shape of theopenings manufactured in a practical case is affected by variations inthe fabrication process such as exposure and etching steps, the anglesof shape of the openings practically manufactured are not necessarilymade exactly 90 degrees and may be between 80 degrees and 100 degrees,for example. The above structure wherein hexagon openings are arrangedin a honey-comb structure can improve the filling factor of the openingsrelative to the substrate surface and maintain the mechanical strength,and thus is preferable. In addition, the openings may be groove-likeopenings. The groove-like openings, if employed, may be formed tointersect one another. The low-permittivity filling members 54 may beformed as an organic siloxane (MSQ) film obtained by partially replacingoxygen of silicon oxide by organic groups such as a methyl group, aporous insulating film wherein minute air gaps having a diameter of 5 nmor less are distributed in the organic siloxane film, and so on. Thelow-permittivity filling members 54 have a preferable relativepermittivity of 3 or less.

There is no restriction on the embedded depth of the low-permittivityfilling members 54 within the semiconductor substrate 51; however, theembedded depth should be as large as possible in the fabrication processin the view point of a higher effective resistance of the semiconductorsubstrate. If the filling depth of the low-permittivity members 54 isrestricted due to the restriction by the practical fabrication process,such as the embedded capability of the low-permittivity members, thedepth of the low-permittivity filling members 54 within the substrate ispreferably 2 μm or above, and more preferably 5 μm or above. FIG. 53shows schematic diagrams wherein the embedded depth of thelow-permittivity filling members 54 is set at 2.5 μm in (a), 5 μm in(b), 10 μm in (c) and 20 μm in (d). FIG. 53( a) shows a layeredinsulating film 52 and an inductor 53. The layered insulating film 52and inductor 53 are also formed in FIGS. 53( b), (c) and (d) similarlyto FIG. 53( a), and thus not specifically depicted in those figures. Inaddition, the height of the low-permittivity filling members 54 measuredtoward the substrate surface in those figures, the location of the topthereof within the layered insulating film etc. are not described herewith reference to FIG. 53, because those configurations are described indetail in the seventh, eighth and ninth embodiments of the presentinvention. In short, the description with reference to FIG. 53 isdirected to the embedded depth of the above low-permittivity fillingmembers 54 in the depthwise direction of the substrate. FIG. 53( e)shows a frequency dependency of the Q-value of the chip inductor 53located on the top interconnect layer for the structures of (a), (b),(c) and (d). Compared to the structure having no embeddedlow-permittivity filling members, the structures shown in (a), (b), (c)and (d) have an improved Q-value. A larger embedded depth of thelow-permittivity filling members 54 allows a higher improvement in theQ-value.

If a semiconductor substrate having a plurality layers with differentspecific resistances, such as described in “Proceedings of IEEE Radioand Wireless Conference, 1998. RAWCON 98” p. 305, is to be used as thesemiconductor substrate 51, it is preferable that the low-permittivitymembers 54 exist from the semiconductor substrate surface down to aroundthe intermediate position of a low-resistance epitaxial layer. Inaddition, it is more preferable that the low-permittivity members 54reach the undermost end of the low-resistance epitaxial layer. It isfurther more preferable that the bottom end of the low-permittivityfilling members 54 penetrate the low-resistance epitaxial layer to reachthe support substrate configuring the undermost layer. Referring to FIG.54, there is shown a schematic diagram depicting that the embedded depthof the low-permittivity filling members 54 within the semiconductorsubstrate 107 including high-resistance epitaxial layer 104,low-resistance epitaxial layer 105 and high-resistance support substrate106 is set at 2.5 μm in (a), 5 μm in (b), 10 μm in (c) and 20 μm in (d)from the substrate surface. FIG. 54( a) shows a layered insulating film52 and an inductor 53. The layered insulating film 52 and inductor 53are also formed in FIGS. 54( b), (c) and (d), similarly to FIG. 54( a),and not specifically depicted in those figures. In addition, the heightof the low-permittivity filling members 54 measured toward the substratesurface in those figures, the location of the top thereof within thelayered insulating film etc. are not described here with reference toFIG. 54, because those configurations are described in detail in theseventh, eighth and ninth embodiments of the present invention. Inshort, the description with reference to FIG. 54 is directed to theembedded depth of the above low-permittivity filling members 54 in thedepthwise direction of the substrate. FIG. 54( e) shows a frequencydependency of the Q-value of the chip inductor 53 located on the topinterconnect layer for the structures of (a), (b), (c) and (d). Comparedto the structure having no embedded low-permittivity filling members,the structures shown in (a), (b), (c) and (d) have an improved Q-value.A higher embedded depth of the low-permittivity filling members 54allows a higher improvement in the Q-value. Further, setting of theembedded depth at 10 μm or above allows a higher improvement factor inthe Q-value. This is probably because the eddy current within thelow-resistance epitaxial layer is further reduced due to theconfiguration wherein the low-permittivity filling members penetratesthe low-resistance epitaxial layer in the case of an embedded depth ofthe low-permittivity filling members being 10 μm or above. Thus, if thesemiconductor substrate having a plurality of layers with differentspecific resistances is used, the embedded depth of the low-permittivityfilling members 54 should be preferably larger than the depth at whichthe low-resistance epitaxial layer is penetrated.

Even if the depth of the low-permittivity filling members 54 b does notreach the undermost end of the low-resistance epitaxial layer due to therestriction by the fabrication process, a higher effective resistancecan be obtained for the substrate resistance, not to mention to thereduction in the substrate capacitance, and a physical separation by alarge distance between the metal interconnects and the semiconductorsubstrate, which constitute the main paths of eddy current occurring inthe semiconductor substrate, thereby achieving the advantages conformingto the object of the present invention.

The low-permittivity filling members 54 may be embedded, in particular,along the periphery of the semiconductor chip, on which an on-chipantenna interconnect may be formed. The on-chip antenna interconnect isformed as an I-character, L-character or U-character shape, or multipleloops, for example. After multi-layered interconnects including windingsof the inductor 53 and on-chip antenna interconnect are formed, thebottom surface of the semiconductor substrate is ground so that thesemiconductor substrate 51 has as small a thickness that is equal to orsmaller than double the depth of the openings in which the fillingmembers 54 are embedded. This achieves a higher resistance for thesubstrate to thereby reduce the substrate current.

Referring to FIG. 2, a semiconductor device according to a secondembodiment of the present invention is similar to the semiconductordevice of the first embodiment except that the semiconductor substrateis ground to the extent wherein the bottom surface of the openings, inwhich the low-permittivity filling members 54 are embedded, is exposedin the present embodiment.

The planar arrangement of the low-permittivity filling members 54 may bea regular arrangement such as square lattice arrangement or obliquedirection arrangement (refer to FIG. 11( a)). In an alternative, it maybe an irregular arrangement such as shown in FIG. 3. The randomarrangement of the low-permittivity filling members 54 reduces theprobability of formation of a linear current path in the RF circuit areaas viewed from the top, thereby increasing the effective substrateresistance R1. Moreover, as shown in FIG. 4, formation of a linearcurrent path which extends across all the width or length of the RFcircuit area may be prevented while regularly arranging thelow-permittivity filling members 54. Furthermore, a so-called honey-combstructure may be used wherein hexagon openings are arranged so as toachieve a higher filling factor.

The low-permittivity filling members 54 may be embedded withinlattice-like trenches, to completely suppress the formation of thecurrent path in the RF circuit area. However, this structure of dividingthe substrate weakens the mechanical strength of the substrate andshould be avoided if the substrate thickness is small.

Referring to FIG. 5, in a third embodiment of the present invention, ahigh-permeability area 300 is provided on the RF circuit area 100. Inthe high-permeability area 300, openings penetrating an interleveldielectric film to reach another interlevel dielectric film are providedin the central area of the windings of an inductor 53 and the peripherythereof in a layered insulating structure 52 including a plurality ofinterlevel dielectric films, and a high-permeability magnetic materialis embedded in the openings to form high-permeability members 55. Inthis structure, if the high-permeability magnetic material embedded hasa conductive bulk state, the openings should meet the condition that theaspect ratio (depth/diameter or length of a side) thereof is “1” orabove for reducing the induced current. If the high-permeabilitymagnetic material embedded is an insulating material or a mixturewherein a micronized soft magnetic material is mixed with an insulatingmaterial (preferably low-permittivity insulating material) as describedbelow, such a condition is unnecessary.

Furthermore, for reducing the parasitic capacitance between the windingsof the inductor 53, the openings may be filled with a low-permittivityinsulating material together with a high-permeability magnetic material.In this case, the high-permeability members 55 should be such that amicronized high-permeability magnetic material is distributed in alow-permittivity insulating material and embedded in the openings.Examples of the preferable insulating material include organic siloxanefilm as described above and a porous insulating film wherein minute airgaps are distributed in the organic siloxane film.

Instead of using the technique wherein the openings are filled with alow-permittivity insulating material in which a micronizedhigh-permeability magnetic material is distributed, thehigh-permeability magnetic members 55 may be such that the wall surfaceof the openings is coated with high-permeability material film by usinga sputtering, CVD or plating technique, and the remaining space of theopenings are filled with the low-permittivity material.

If the high-permeability magnetic members 55 are configured by aconductive bulk material, large-size openings may be formed in the areain which the high-permeability magnetic members are formed, and theopenings may be filled with a low-permittivity insulating material. Inthis case, openings for embedding therein a high-permeability magneticmaterial are formed in the low-permittivity insulating film, and theopenings are filled with a soft magnetic material as by using asputtering or electrolytic plating technique. The high-permeabilitymagnetic members 55 may be provided in an area other than theinductor-forming area. In this case, the high-permeability magneticmembers 55 act for a magnetic shield function.

Referring to FIG. 6, a fourth embodiment of the present invention issimilar to the third embodiment except that a high-permeability member55 is provided with, in addition to the rod members 55 a of thehigh-permeability member 55, which extend normal to the substratesurface, and a plane member 55 b for covering top of the rod members 55a and coupling together the rod members 55 a in the present embodiment.The plane member 55 b provided for the high-permeability magneticmembers 55 increases the permeability in the periphery of the windingsof the inductor 53, to further increase the inductance or further reducethe size of the inductor 53, and also reduces the induced current ofother interconnects.

In the depicted example, the plane member 55 b of the high-permeabilitymember 55 is provided on top of the rod members 55 a; however, it may beprovided on the bottom portion of the rod member 55 a. In analternative, both the top and bottom of the rod members 55 b may beprovided with the plane members.

In the semiconductor devices of the first through fourth embodiments,the inductor can be reduced in size thereof and has a higherperformance, and in addition, the passive element thus reduced in sizeand having a higher performance can be mounted on a single mixed-circuitchip on which active elements such as a CMOS circuit are provided. Thus,according to the semiconductor device of the present invention, amixed-circuit chip can be achieved including an RF circuit having areduced loss as well as reduced noise propagation and a digital circuit(including a memory section such as SRAM).

In a mixed-circuit chip mounting thereon a RF communication function,signal transfer between the chips can be achieved using radio USB, radioWLAN or UWB communication. When configuring a system including aplurality of digital logic chips in the conventional technique, aplurality of chips are mounted on a printed circuit board, wherein along time as well as a large amount of work is needed for solving theproblems of signal delay or signal coupling.

According to the semiconductor device of the present invention, as shownin FIG. 7, by preparing a plurality of RF circuit/digital circuit-mixedchips each mounting thereon a plurality of RF communication circuitareas 61, a plurality of digital baseband areas 62 and a memory area 63,the signal transfer between these chips can be achieved without wires.Thus, the printed circuit board can be specialized solely for alow-noise power supply, thereby reducing the amount of design work. Inaddition, the restriction on the chip arrangement can be significantlyreduced.

FIG. 30 is a structural drawing showing a fifth embodiment of thepresent invention. According to the fifth embodiment of the presentinvention, a plurality of interconnect layers 85 including at least twolayers are formed on the above low-capacitance substrate, a plurality ofvia-plugs 86 are formed all over the area of the interconnect layers,and the plurality of interconnect layers are electrically connected inparallel to form an inductor. Numeral 19 denotes a high-permeabilityisolation region formed in an area including the core of the inductorand the periphery thereof.

FIG. 31 shows the top plan view of the inductor interconnect and asectional view thereof. Via-plugs 86 a, 86 b connecting together aplurality of interconnect layers are shown therein. In this explanatoryview of FIG. 31, a spiral type is shown as the planar shape of theinductor 85; however, known circular shape or octagon shape may be usedas the planar shape of the inductor 85. In general, the number ofvia-plugs is limited based on the restriction as to the shape, size,arrangement, allowable number of arrangement depending on thesemiconductor device manufacturing process or design. For reducing theresistance of the interconnect layers connected together in parallel, itis preferable to connect together the plurality of interconnect layersby using the via-plugs in number as large as that allowed in the design.The number of via-plugs 86 a, 86 b shown in the explanatory drawing ofFIG. 31 is obviously smaller than the number of via-plugs allowable inthe restriction by the semiconductor device manufacturing processgenerally used and the design. The reason is that the object of thedrawing is to show the principle of the present invention in theconceptual figure, and thus the present invention is not restricted toany of the arrangement, shape, number etc. of the via-plugs shown inFIG. 31.

The connection of a plurality of interconnect layers together inparallel corresponds to an increase in the thickness of the interconnectlayer, in the view point of the electric circuit theory, as compared tothe case of using a single interconnect layer to form an inductor,whereby the resistance loss of the inductor line can be reduced. Use ofthe plurality of interconnect layers generally reduces the distancebetween the interconnect layers and the substrate as compared to thecase of using the single topmost interconnect layer, whereby thecapacitance between the interconnect layers and the substrate isincreased. However, according to the present embodiment, alow-capacitance substrate region is formed in the substrate, to therebysuppress the influence by the increase in the capacitance. Thus, aninductor element is obtained wherein the connection of the plurality ofinterconnect layers together in parallel reduces the resistance loss andyet suppresses the increase in the capacitance.

FIG. 32 is a structural drawing showing a sixth embodiment of thepresent invention. According to the sixth embodiment of the presentinvention, an inductance 91 is formed wherein ends of at least twolayers out of a plurality of interconnect layers are connected togetherin series by using a plurality of via-plugs. FIG. 33 shows the top planview of an inductor line. In this explanatory view of FIG. 33, a spiraltype is shown as the planar shape of the inductor 91; however, a knowncircular shape or octagon shape may be used as the planar shape of theinductor. Connection of a plurality of interconnect layers 87, 88together in series corresponds to an increase in the line length of theinductor line, whereby an inductor element having the same inductancecan be formed in a reduced occupied area as compared to the case ofusing the single interconnect layer to form an inductor. Use of theplurality of interconnect layers generally reduces the distance betweenthe interconnect layers and the substrate as compared to the case ofusing the single topmost interconnect layer, whereby the capacitancebetween the interconnect layers and the substrate is increased. However,according to the present embodiment, a low-capacitance substrate regionis formed in the substrate, to thereby suppress the influence by theincrease in the capacitance. Thus, an inductor element is obtainedhaving a reduced occupied area and suppressing the increase in thecapacitance.

In the present embodiment, if the plurality of interconnect layers aredisposed to overlap together in the vertical direction, there arises aparasitic capacitance therebetween. More specifically, the parasiticcapacitance corresponds to an inter-line capacitance Cp shown in theequivalent circuit of FIG. 27. For reducing this parasitic capacitance,different line widths are employed for the interconnect layers 87, 88overlapping together in the vertical direction, thereby allowing theparasitic capacitance between the interconnects to be reduced. Moreover,the interconnects overlapping together in the vertical direction out ofthe plurality of interconnect layers configuring a single inductorelement by a serial connection thereof should preferably have thedirections of the currents which do not oppose each other, forprevention of a negative mutual inductance from occurring therebetween.FIGS. 33 to 38 exemplarily show the arrangement of the plurality ofinterconnect layers for achieving such an object.

In general, the number of via-plugs 86 is limited based on therestriction as to the shape, size, arrangement, allowable number ofarrangement depending on the semiconductor device manufacturing processor design. For reducing the resistance of the connection usingvia-plugs, it is preferable to connect together the plurality ofinterconnect layers by using the via-plugs in number as large as thatallowed in the design. The number of via-plugs shown in the explanatorydrawings of FIGS. 33 to 38 is obviously smaller than the number ofvia-plugs allowable in the restriction by the semiconductor devicemanufacturing process generally used and the design. The reason is thatthe object of the drawings is to show the principle of the presentinvention in the conceptual figure, and thus the present invention isnot restricted to any of the arrangement, shape, number etc. of thevia-plugs shown in FIGS. 33 to 39.

A seventh embodiment of the present invention shown in FIG. 39 isapplied to a semiconductor device wherein metallic interconnectscontaining copper as the main component thereof are formed using adamascene technique on a semiconductor substrate having alow-capacitance substrate region. On a first interlevel dielectric film4 are formed a first stopper insulating film 92 and a second stopperinsulating film 93 each including at least silicon and at least oneelement other than the elements included in the first interleveldielectric film 4. Here, a metallic interconnect 10 formed in the secondinterlevel dielectric film 9, first stopper insulating film 92 andsecond stopper insulating film 93 overlying the low-capacitancesubstrate region has a flat bottom surface.

In the present embodiment, copper or an alloy containing copper as themain component thereof, if used as the main component of themulti-layered interconnects, affords the advantages of the embodiment.The interconnection structure made of copper or containing copper as themain component thereof is generally formed by a so-called damascenetechnique. The damascene technique, if used for forming themulti-layered interconnects in the seventh embodiment, provides theadvantage of the present embodiment. Since only the structure of thelow-capacitance substrate region formed in the semiconductor substrateis different from those in the embodiments up to the sixth embodiment,the structure of this specified region will be extracted and described.In addition, the interconnect materials including copper as the maincomponent thereof and fabrication method thereof are assumed as thecurrent mainstream materials and method. The detail of the method forforming the interconnects containing copper as the main component willnot be specifically described because the material, structure andfabrication method of the interconnect containing copper as the maincomponent in the present embodiment do not have an influence on thepresent invention. The seventh embodiment of the present invention willbe described hereinafter with reference to the drawings.

In FIG. 39, on the first interlevel dielectric film 4 are formed thefirst stopper insulating film 92 and second stopper insulating film 93each including at least silicon and at least one element other then theelements in the first interlevel dielectric film 4. The stopperinsulating films are preferably made of a material including at leastsilicon and providing a sufficient selectivity ratio during a CMPtreatment of the low-permittivity film 7 configuring thelow-permittivity insulator rods 8 and during a plasma-enhanced etchingtreatment for the second interlevel dielectric film 9. Morespecifically, if a material having a lower permittivity than a siliconoxide film, such as SiO₂, a material wherein SiO₂ is doped with elementsuch as boron or phosphorous, a material wherein oxygen of silicon oxidefilm is replaced by hydrogen or methyl group, silica (SiOC) or SiOCHadded with carbon is to be used, the stopper insulating films 92, 93 arepreferably made of a material including at least silicon and nitrogen,such as SiN, SiON or SiCN. If a material having a lower permittivitythan a silicon oxide film, such as a material wherein oxygen of siliconoxide film is replaced by hydrogen or methyl group, or silica (SiOC) orSiOCH added with carbon is to be used, the stopper insulating films 92,93 is preferably made of a material including silicon and nitrogen, suchas SiN, SiON and SiCN. The stopper insulating films 92, 93 may have thesame constituent elements and the same composition, and thus may be madeof the same insulating material. In this case, the interface between thefirst stopper insulating film 92 and the second stopper insulating film93 shown in FIG. 37 may not be clearly observed as such even if ascanning electron microscope or transmission electron microscope isused. The present embodiment features that the first metallicinterconnect 10 formed in the first stopper insulating film 92, secondstopper insulating film 93 and second interlevel dielectric film 9overlying the low-capacitance substrate region has a flat bottomsurface, and the top surface of a low-permittivity insulator rod justunderlying the metallic interconnect 10 and the top surface of anotherlow-permittivity insulator rod not underlying the metallic interconnect10 are not flush with each other.

The seventh embodiment can be applied to all the first through sixthembodiments so long as copper or an alloy including copper as the maincomponent is used for the material of the multi-layered interconnects.

An eighth embodiment of the present invention is applied to asemiconductor device wherein a metallic interconnect containing copperas the main component thereof is formed using a damascene technique on asemiconductor substrate including therein a low-capacitance substrateregion. On the first interlevel dielectric film 4 are formed a firststopper insulating film 92 and a second stopper insulating film 93 eachincluding at least silicon and at least one element other than theelements in the first interlevel dielectric film 4. The metallicinterconnect 10 formed in the second interlevel dielectric film 9, firststopper insulating film 92 and second stopper insulating film 93overlying the low-capacitance substrate region has a flat bottomsurface, and cap insulating films 94 having a higher permittivity and ahigher mechanical strength than the low-permittivity insulator rods 8are formed on the top end of the respective low-permittivity insulatorrods in the top portion of the openings for the low-permittivityinsulator rods 8 located in the low-capacitance substrate region.

The present embodiment, if copper or an alloy containing copper as themain component thereof is used therein for the material of themulti-layered interconnects, achieves the advantage thereof. Theinterconnection structure including copper or an alloy containing copperas the main component thereof is generally formed using the damascenetechnique. The damascene technique, if used for forming themulti-layered interconnects in the eighth embodiment, provides theadvantage of the present embodiment. Since only the structure of thelow-capacitance substrate region formed in the semiconductor substrateis different from those in the embodiments up to the sixth embodiment,the structure of this specified region will be extracted and described.In addition, the interconnect materials including copper as the maincomponent thereof and fabrication method thereof are assumed as thecurrent mainstream materials and method. The detail of the method forforming the interconnects containing copper as the main component willnot be specifically described because the material, structure andfabrication method of the interconnect containing copper as the maincomponent in the present embodiment do not have an influence on thepresent invention. The eighth embodiment of the present invention willbe described hereinafter with reference to the drawings.

FIG. 40 is a structural drawing showing the eighth embodiment of thepresent invention. In the present embodiment, on the first interleveldielectric film 4 are formed a first stopper insulting film 92 and asecond stopper insulating film 93 each including at least silicon and atleast one element other than the elements in the first interleveldielectric film 4. The stopper insulating films are preferably made of amaterial including at least silicon and providing a sufficientselectivity ratio during a plasma-enhanced etching of thelow-permittivity film 7 configuring the low-permittivity insulator rods8 and the second interlevel dielectric film 9. More specifically, if amaterial having a lower permittivity than a silicon oxide film, such asSiO₂, a material wherein SiO₂ is doped with element such as boron orphosphorous, a material wherein oxygen of silicon oxide film is replacedby hydrogen or methyl group, silica (SiOC) or SiOCH added with carbon isto be used, the stopper insulating films 92, 93 are preferably made of amaterial including at least silicon and nitrogen, such as SiN, SiON orSiCN. If a material having a lower permittivity than a silicon oxidefilm, such as a material wherein oxygen of silicon oxide film isreplaced by hydrogen or methyl group, or silica (SiOC) or SiOCH addedwith carbon is to be used, the stopper insulating films 92, 93 ispreferably made of a material including silicon and nitrogen, such asSiN, SiON and SiCN. The stopper insulating films 92, 93 may have thesame constituent elements and the same composition, and thus may be madeof the same insulating material. In this case, the interface between thefirst stopper insulating film 92 and the second stopper insulating film93 shown in FIG. 40 may not be clearly observed as such even if ascanning electron microscope or transmission electron microscope isused.

In the present embodiment, cap insulating films 94 having a higherpermittivity and a higher mechanical strength than the low-permittivityinsulator rods 8 are formed on the top end of the respectivelow-permittivity insulator rods in the top portion of the openings forthe low-permittivity insulator rods 8.

The present embodiment features that the first metallic interconnect 10formed in the first stopper insulating film 92, second stopperinsulating film 93 and second interlevel dielectric film 9 overlying thelow-capacitance substrate region has a flat bottom surface, and the topsurface of the cap insulating film formed on a low-permittivityinsulator rod just underlying the metallic interconnect 10 and the topsurface of the cap insulating film formed on another low-permittivityinsulating film not underlying the metallic interconnect 10 are notflush with each other.

The eighth embodiment can be applied to all the first through sixthembodiments so long as copper or an alloy including copper as the maincomponent thereof is used for the material of the multi-layeredinterconnects.

A ninth embodiment of the present invention provides the advantages ofthe present invention, if aluminum or aluminum including a minute amountof silicon or a minute amount of copper, now used as the mainstreammaterial, is used for the material of the multi-layered interconnects.Since only the structure of the low-capacitance substrate region formedin the semiconductor substrate is different from those in theembodiments up to the sixth embodiment, the structure of this specifiedregion will be extracted and described. In addition, the interconnectmaterials including aluminum as the main component thereof andfabrication method thereof are assumed as those now used as themainstream materials and method. Since the material, structure andfabrication method of the interconnect containing copper as the maincomponent in the present embodiment do not have an influence on thepresent invention, the detail thereof will not be specificallydescribed. The ninth embodiment of the present invention will bedescribed hereinafter with reference to the drawings.

FIGS. 41( a) and (b) are structural drawings showing the ninthembodiment of the present invention. The present embodiment featuresthat the top surface of the low-permittivity insulator rods 8 is locatedon the lower position than the top surface of the W contact plugs 5. Capinsulating films 94 are formed on the top end of the low-permittivityinsulator rods in the top portion of the openings for thelow-permittivity insulator rods 8 configuring the low-capacitancesubstrate regions. In formation of the aluminum interconnects generallyused, after a metal compound including titanium etc. and a main materialincluding at least aluminum are deposited using a sputtering techniqueetc., patterning is conducted using the photoresist, and a desired shapefor the interconnects is obtained using plasma-enhanced etching. If theexposed top surface of the low-permittivity insulator rods 8 issubjected to metallic sputtering thereon or exposed to etching plasma,there may arise property modification wherein the sputtered metal isdistributed into the low-permittivity rods, or some elements of thelow-permittivity material configuring the low-permittivity rods aredetached therefrom due to the etching plasma whereby the relativepermittivity of the low-permittivity material increases. The advantageof the present embodiment is such that the top surface of thelow-permittivity insulator rods 8 is protected by the cap insulatingfilms 94 against the sputtering and etching plasma to thereby preventthe above property modification. The ninth embodiment can be applied tothe first through sixth embodiments of the present invention whereinaluminum or a metallic compound containing aluminum as the maincomponents thereof is used as the material for the multi-layeredinterconnects.

EXAMPLES

Preferable examples of the present invention will be described in detailwith reference to the drawings.

First Example

FIG. 8( a) is a top plan view showing the first example of the presentinvention, and FIG. 8( b) is a sectional view taken along line A-A′ inFIG. 8( a). On a silicon semiconductor substrate are provided an RFcircuit area (high-frequency signal processing circuit area) 100 and adigital circuit area 200. MOSFETs 3 are formed in the regions isolatedby shallow-trench-isolation film 2 on the silicon substrate 1, toconfigure CMOS circuits. In the silicon substrate of the RF circuit area100 are located a plurality of low-permittivity insulator rods 8 inwhich low-permittivity insulator is embedded. In the present example,the low-permittivity insulator rods 8 penetrate the first interleveldielectric film isolating the CMOS transistors and multi-layeredinterconnects to reach the internal of the silicon substrate. Morespecifically, the low-permittivity insulator rods are formed after allthe CMOS transistor forming steps are finished; in other words, afterall the high-temperature heat treatment steps necessary for forming theMOS transistors are finished. Thus, an insulating film having a lowerpermittivity than the silicon oxide film can be embedded.

After all the device forming steps are finished, the silicon substrate 1is ground to be thin until the bottom surface of the low-permittivityinsulator rods are exposed. The thin substrate structure increases theeffective resistance of the silicon substrate, and the arrangement ofthe low-permittivity insulator rods obtains the low-capacitancesubstrate region, thereby reducing the noise propagating through thesubstrate and also reducing the loss.

The source/drain regions of the MOSFETs 3 are connected to first-levelcopper interconnects 10 embedded within a second interlevel dielectricfilm 9 via tungsten (W) contact plugs 5 formed within the firstinterlevel dielectric film 4. A third interlevel dielectric film 11 anda fourth interlevel dielectric film 13 are formed thereon whichrespectively embed therein a second-level copper interconnects 12 and athird-level copper interconnects 14. In the low-capacitance substrateregion wherein low-permittivity insulator rods 8 are arranged, aninductor 40 is formed using the third-level copper interconnects 14 andsecond-level copper interconnects 12. The arrangement of the inductor inthe low-capacitance substrate region reduces the coupling capacitance(Cox/2) between the inductor and the substrate, thereby reducing loss ofthe inductor.

On the fourth interlevel dielectric film 13 is formed a fifth interleveldielectric film 15, on the fifth interlevel dielectric film 15 in the RFcircuit area 100 is formed a depression, and openings are formed topenetrate the fifth interlevel dielectric film 15 and fourth interleveldielectric film 13. A soft magnetic substance including a NiFe alloy asthe main body is embedded within the depression and openings to formhigh-permeability isolation regions 19. The high-permeability isolationregions 19 are formed in an area including the core of the inductor 40and the periphery thereof. This reduces the size of the inductor. Thesize reduction of the inductor affords reduction of the inductor linelength to thereby reduce Rs and Cox/2. In other words, the sizereduction of the inductor not only reduces the occupied area factorthereof, but also improves the performance thereof. Thehigh-permeability isolation regions may be formed in an area other thanthe inductor forming area, and in such a case, they act for a functionof magnetic shielding for the RF circuit elements. The fifth interleveldielectric film 15 is covered by a cover film 20.

Next, a method for manufacturing the semiconductor device of the firstexample will be described with reference to FIGS. 9 to 18. In each ofFIGS. 9 to 18, (a) represents a top plan view and (b) represents asectional view taken along line A-A′ therein.

As shown in FIG. 9, a shallow opening having a depth of 300 nm to 500 nmis formed on the silicon substrate 1 except for element-forming areas1A, and a silicon oxide film is embedded within the opening to therebyform a shallow-trench element isolation film 2. Subsequently, as shownin FIG. 10, p- and n-wells (not shown) are formed in the element-formingareas 1A, followed by growing gate insulating films, forming gateelectrodes, forming diffused regions and silicifying the same, therebyforming MOSFETs 3 configuring CMOS digital circuits and CMOS RFcircuits. Thereafter, a silicon oxide film is deposited and planarizedusing a CMP technique to form the first interlevel dielectric film 4,followed by forming via-holes reaching the gate electrodes and diffusedregions, and filling the same with tungsten to form W contact plugs 5. Amulti-oxide technique may be used for the gate insulating film for theCMOS digital circuits and CMOS RF circuits. It is important to completeall the high-temperature heat treatment steps at temperatures equal toor above 700 degrees C. in this transistor forming process.

Thereafter, a silicon oxide film (not shown) having a thickness ofaround 50 nm is formed, if needed, followed by forming openings 6penetrating the first interlevel dielectric film 4 and element isolationfilm 2 in the RF circuit area 100 to reach the internal of the siliconsubstrate 1. Although there is no restriction on the shape and depth ofthe openings 6, the openings may have a diameter of 1 to 3 μm and adepth of 5 to 30 μm, for example. Although three is no restriction onthe arrangement of the openings, the openings may be arranged in anoblique direction, for example. The openings may include groove-likeones. Moreover, the openings may have a honey-comb structure whereinhexagon openings are arranged to obtain a higher filling factor.

Thereafter, as shown in FIG. 12, a low-permittivity insulating film 7 isformed so as to fill the openings 6. Although there is no restriction onthe material for the low-permittivity insulating film, it is necessarythat the low-permittivity insulating film have a lower permittivity thanat least the silicon oxide film. For example, a coating insulating film,such as made of ladder oxide wherein oxygen of a silicon oxide film isreplaced by hydrogen, or MSQ wherein such oxygen is replaced by methyl,can be used. Moreover, a plasma-enhanced CVD film, such as made ofsilica (SiOC) or SiOCH added with carbon, may be also used. Furthermore,a porous film wherein air gaps having a diameter of 10 nm or less isdispersed in an insulating film may also be used. Instead of filling theentire openings 6 with the low-permittivity insulating film, a thinsilicon oxide film or silicon nitride film may be grown using a thermalCVD technique, ozone-oxidizing CVD technique or plasma-enhanced CVDtechnique on the wall of the openings, followed by embedding alow-permittivity insulating film therein.

Thereafter, as shown in FIG. 13, the low-permittivity insulating film onthe interlevel dielectric film is removed by a CMP technique to therebyform in the silicon substrate the low-permittivity insulator rods 8,wherein the low-permittivity insulating film is embedded within theopenings. Although the entire portion of the low-permittivity insulatingfilm 7 on the first interlevel dielectric film 4 is removed by the CMPtechnique in the embodiment, part of them may be left as an elementisolation film between the multi-layered interconnects.

Thereafter, the second interlevel dielectric film 9 is grown, and aninterconnection trench exposing therethrough top of the W contact plugs5 is formed therein. A barrier metal, such as Ta/TaN or TiW, having athickness of around 25 nm and a seed copper film having a thickness ofaround 100 nm are grown in the interconnection trench, followed bygrowing thereon a copper film by an electrolytic plating technique usingthe seed copper film as an electrode. By selectively removing the copperfilm and barrier metal film by using a CMP technique, the first-levelcopper interconnects 10 having a damascene structure are formed withinthe second interlevel dielectric film 9. There is no restriction on thematerial for the second interlevel dielectric film 9, and a siliconoxide film, ladder oxide, MSQ, SiOCH or porous film may be used for thispurpose. On top of the damascene copper interconnects is formed a capfilm such as made of SiCN or SiC for prevention of copper diffusion.

Thereafter, by iteratively growing an insulating film, forminginterconnection trench and via-holes and filling the via-holes with acopper film, as shown in FIG. 15, a multi-layered interconnectionstructure is formed including the third interlevel dielectric film 11embedding therein the second-level copper interconnects 12, and thefourth interlevel dielectric film 13 embedding therein the third-levelcopper interconnects 14. In the present example, the inductor 40 isformed using the third-level interconnects 14 and the second-levelinterconnects 12. Although there is no restriction on the number ofinterconnect layers for configuring the inductor, it is necessary toallow the same to overlie the low-permittivity substrate region, whereinat least the low-permittivity insulator rods 8 embedded in the siliconsubstrate are arranged. This arrangement of the inductor reduces thecoupling capacitance (Cox/2) between the inductor and the substrate andthus reduces the loss.

Thereafter, as shown in FIG. 16, the fifth interlevel dielectric film 15is grown on the interconnect layers configuring the inductor.Depressions 16 are then formed on the surface of the fifth interleveldielectric film 15 in the RF circuit area 100, followed by formingopenings 17 penetrating the fifth interlevel dielectric film 15 andfourth interlevel dielectric film 13 to reach the third interleveldielectric film 11. It should be noted that the surface of the fifthinterlevel dielectric film 15 may be covered with a silicon oxynitridefilm.

Thereafter, as shown in FIG. 17, a soft magnetic material film 18filling the depressions 16 and openings 17 is formed so as to cover thefifth interlevel dielectric film 15. As the soft magnetic material film18, a FeNi film is grown using an electrolytic plating technique on aTa/TiW barrier metal (TiW is the underlying film), which has beendeposited by sputtering. A buffer metal, such as Ru or Ir, having athickness of around 1 nm to 10 nm may be interposed between the barriermetal and FeNi. The soft magnetic material film may be formed using acoating film wherein minute particles of soft magnetic metal such asNiFe or soft magnetic ferrite such as (Ni, Zn)FeO are distributed withina low-permittivity insulating film. In this case, the particle diameterof the soft magnetic minute particles is preferably equal to or belowaround 500 nm. By removing a portion of the soft magnetic material filmon the fifth interlevel dielectric film 15 by using a CMP technique,high-permeability isolation regions 19 each including a flat planarmember and a rod member which is normal to the substrate surface areformed (FIG. 18). Formation of the high-permeability isolation regions19 in the core region of the inductor allows even the small-sizedinductor to have an increased inductance (L). For example, in case ofNiFe having a relative permeability of 10 to 100, a size reduction ofthe inductor in terms of area ratio of 1/5 can be obtained for the sameinductance.

Thereafter, a cover film 20 is formed covering the fifth interleveldielectric film 15 in which the high-permeability isolation regions 19are formed, followed by grinding the bottom surface of the siliconsubstrate to expose the bottom of the low-permittivity insulator rods 8,whereby the semiconductor device of the present example shown in FIG. 8can be obtained.

Second Example

Referring to FIG. 19( a), the second example of the present invention issimilar to the first example shown in FIG. 8 except thathigh-permeability isolation rods 21 without including a planar memberare formed in the core of the inductor and the periphery thereof insteadof the high-permeability isolation regions (19) each including a planarmember and a rod and that the bottom surface of the low-permittivityinsulating rods 8 is not exposed from the bottom surface of thesubstrate.

The fabrication method of the present example is similar to that of thefirst example in the steps up to the step shown in FIG. 15. Thereafter,the fifth interlevel dielectric film 15 is grown on the interconnectlayers configuring the inductor 40, followed by forming openingspenetrating the fifth interlevel dielectric film 15 and the fourthinterlevel dielectric film 13 to reach the third interlevel dielectricfilm 11. The diameter of the openings is generally 1 μm to 2 μm, but notlimited thereto. It is important here that the depth of the openings islarge with respect to the diameter thereof, i.e., the aspect ratio isequal to or higher than 1. It should be noted that the fifth interleveldielectric film may be covered with a silicon oxynitride film.

Thereafter, barrier metal and NiFe soft magnetic metal are grown, andthe metallic films on the fifth interlevel dielectric film is removed byCMP, whereby high-permeability isolation rods 21 penetrating the fifthinterlevel dielectric film 15 and fourth interlevel dielectric film 13to reach the third interlevel dielectric film are formed. In analternative, a coating material wherein minute particles of a softmagnetic material such as (Ni, Zn)Fe₂O₄ are dispersed in thelow-permittivity insulating film may be applied thereon, and the coatingfilm is removed by a CMP technique to form the high-permeabilityisolation rods 21. Thereafter, the cover film 20 is deposited and thebottom surface of the silicon substrate is ground, whereby thesemiconductor device of the present embodiment can be obtained. Thegrinding should preferably be performed so that the silicon substratehas as small a thickness as two-fold or smaller than the length of thelow-permittivity insulating rods within the substrate. For example,assuming that the low-permittivity insulating rods obtained by embeddingMSQ having a relative permittivity of 2.5 in the openings having a 3 μmdiameter and a 20 μm depth are arranged in an oblique direction at a 6μm pitch, grinding the silicon substrate down to as small a thickness as40 μm reduces the coupling capacitance between the inductor and thesubstrate by 50%.

Third Example

Referring to FIG. 20, the third example of the present invention issimilar to the first example shown in FIG. 8 except that fourth-levelcopper interconnects are formed in the fifth interlevel dielectric film15 overlying the windings of the inductor 40, a sixth interleveldielectric film 23 is formed thereon and fifth-level copperinterconnects are formed therein.

The fabrication method of the present example is similar to that of thefirst example in the steps up to forming the fifth interlevel dielectricfilm 15. After depositing the fifth interlevel dielectric film 15,interconnection trenches and via-holes are formed in the fifthinterlevel dielectric film 15, followed by forming a copper film andperforming CMP thereof to form the fourth-level copper interconnects 22.Thereafter, high-permeability isolation regions 19 are formed using amethod similar to that of the first example. Further, the sixthinterlevel dielectric film 23 and fifth-level copper interconnects 24are formed, and a cover film 20 is formed thereon. Grinding the bottomsurface of the substrate achieves the semiconductor device of thepresent example.

Fourth Example

Referring to FIG. 21, the fourth example of the present invention issimilar to the third example except that high-permeability isolationplanes 25 connected to the high-permeability isolation regions 19 areembedded within the depressions formed on the surface of the thirdinterlevel dielectric film 11.

The fabrication method of the present example is similar to that of thethird example in the steps up to forming the third interlevel dielectricfilm 11. After depositing the third interlevel dielectric film 11,interconnection trenches and via-holes are formed in the thirdinterlevel dielectric film 11, followed by forming a copper film andperforming CMP thereof to form the second-level copper interconnects 12.Thereafter, depressions are formed in the third interlevel dielectricfilm 11, barrier metal and NiFe soft magnetic metal are grown and aportion of the metallic films on the third interlevel dielectric film 11is removed by CMP, thereby forming high-permeability isolation planes25. The subsequent steps are similar to those in the third example.

Fifth Example

Referring to FIG. 22, the fifth example of the present invention isconfigured as a semiconductor device including CMOS transistors formedon a SOI (silicon on chip) substrate. On the SOI substrate are disposedan RF circuit area 100 and a digital circuit area (not shown). Asunderstood from FIG. 22, n-channel or p-channel MOSFETs 3 configured asthin-film transistors are formed on the silicon substrate 1 with anintervention of an embedded oxide film 27. The MOSFETs 3 are covered bya first interlevel dielectric film 4, on which a first-levelinterconnects 10 a connected to source/drain regions of the MOSFETs 3via contact plugs 5 a are formed.

The periphery of the MOSFETs 3 is provided with openings penetrating thefirst interlevel dielectric film 4 and embedded oxide film 27 to reachthe internal of the silicon substrate 1. A low-permittivity insulatingmaterial is embedded in the openings to form low-permittivity insulatingrods 8. Although not depicted in the figure, one or a plurality ofinterlevel dielectric films are formed on the first interleveldielectric film in the present example, similarly to the first throughfourth examples. An inductor and high-permeability isolation regions areformed in the interlevel dielectric films in the RF circuit area.

Sixth Example

Referring to FIG. 23, the sixth example of the present invention is suchthat the present invention is applied to a compound semiconductordevice. As shown in FIG. 23, on a semi-insulating GaAs substrate 20 areformed an n⁺-GaAs layer 30 and an n⁻-GaAs layer 31 configuring collectorregions in an area encircled by H⁺-doped high-resistance areasconfiguring isolation regions, and a p⁺-GaAs layer 32 configuring baseregions is formed thereon. An n-AlGaAs layer configuring the emitterregions and an n-InGaAs layer configuring the contact layer are formedthereon. On the n⁺-GaAs layer 30 is formed a Au/Ni/AuGe layer 35configuring the collector electrodes, and on the p+-GaAs layer 32 isformed a Au/Pt/Ti layer 36. On the n-InGaAs layer 34 are formed a WSilayer configuring the emitter electrodes and a Au/Pt/Ti layer 38.

H⁺-doped high-resistance regions 29 and transistors are covered by thefirst interlevel dielectric film 4, on which a first-level interconnects10 a connected to electrodes of the transistors via contact plugs 5 aare formed.

The periphery of the transistors is provided with openings penetratingthe first interlevel dielectric film 4 and H⁺-doped high-resistanceregions to reach the internal of the semi-insulating GaAs substrate 28.The openings are filled with a low-permittivity insulating material toform low-permittivity insulating rods 8. Although not depicted in thefigure, one or a plurality of interlevel dielectric films are formed onthe first interlevel dielectric film 1 in the present example, similarlyto the first through fourth examples. An inductor and high-permeabilityregions are formed in the interlevel dielectric films in the RF circuitarea 100.

Seventh Example

FIG. 24( a) is a top plan view showing the seventh example of thepresent invention, and FIG. 24( b) is a sectional view taken along lineA-A′ in FIG. 24( a). In the present example, the present invention isapplied to a semiconductor device including an on-chip antenna. In FIG.24, the parts equivalent to the parts of the first example are denotedby similar reference numerals, and thus will be omitted for a duplicateddescription. In the present example, a peripheral high-resistance area400 is provided on the periphery of the semiconductor chip, and theinner side of the semiconductor chip is provided with a RF circuit area100 and a digital circuit area 200. In the peripheral high-resistancearea 400 are formed low-permittivity insulating rods 8 penetrating thefirst interlevel dielectric film 4 and shallow-trench isolation film 2to reach the internal of the silicon substrate 1. The on-chip antennalinterconnect 41 is formed on the peripheral high-resistance area 400 byusing the fourth-level copper interconnects within the fifth interleveldielectric film 15.

The on-chip antenna interconnect 41 is connected to MOSFETs formed inthe RF circuit area 100 via the multi-layered interconnects.

An antenna for receiving radio waves is dispensable to the semiconductorchip having a wireless function. There is a technique wherein a chiphaving the antenna formed on an insulating film such as alumina ceramicsis separately manufactured in advance, and externally attached toanother semiconductor chip having an RF circuit. In this technique,however, there are technical problems that the inter-chip connectionsincur a loss and noise entering therethrough, and that a size reductionis difficult to achieve. Compared thereto, the antenna formed on thechip solves those problems. In the conventional technique, however, evenif the antenna is provided on the silicon semiconductor chip forexample, a higher-efficiency antenna cannot be formed due to the radioshielding by the low resistance of the silicon substrate.

In the seventh example, as shown in FIG. 24, the peripheralhigh-resistance area 400 having a high resistance and a low permittivityis formed, wherein the low-permittivity insulating rods 8 are embeddedin the periphery of the chip, and the antenna is configured by thetopmost interconnect layer. The arrangement in the peripheral area is toimprove the transmitting/receiving efficiency by increasing the lengthof the antenna. It is to be noted that although the antenna having aloop shape is formed in the peripheral area of the chip, the shape ofthe antenna is not limited thereto. The antenna may have an I-shapewherein it is located in the vicinity of a single side of the chip, anL-shape wherein it is located in the vicinity of two sides, a U-shapewherein it is located in the vicinity of three sides, or a multiple-loopstructure.

Eighth Example

FIG. 25( a) is a top plan view showing the eighth example of the presentinvention, and FIG. 25( b) is a sectional view taken along line A-A′ inFIG. 25( a). The present example is similar to the seventh example shownin FIG. 24 except that the antenna interconnect has a multi-layeredstructure and that a grounded shield interconnect 42 is additionallyprovided in the radially-inward position of the on-chip antenna havingthe multi-layered structure. The multi-layered antenna interconnect issuch that a multiple of antenna interconnect layers embedded in theslit-like openings, which turn around the periphery of the chip andpenetrate the interlevel dielectric films, are layered one on another.More specifically, it has a structure wherein a wall of the antennainterconnect is formed from the topmost interconnect layer to theundermost interconnect layer in the peripheral area of the chip. It isto be noted that the antenna interconnects need not necessarily beformed from the topmost interconnect layer to the undermost interconnectlayer. The antenna interconnect may be configured by a plurality oflayers such as two layers including the topmost layer. In the presentexample, the shield interconnect 42 is provided in the radially-inwardposition of the antenna interconnects, and the shield interconnect arealso formed from multi-layered interconnects embedded within slit-likeopenings which turn around. More specifically, a wall of the shieldinterconnect is formed from the topmost layer interconnects to theundermost layer interconnects, and thus has a structure wherein the wallshields the antenna interconnects away from the electromagnetic noise.It is to be noted that the multi-layered antenna interconnect andmulti-layered shield interconnect have also a function of blocking thewater entering from outside the chip.

Ninth Example

Next, a fabrication method for forming the structure of the seventhexample will be described with reference to FIGS. 42 to 45. Thefabrication method is an example of achieving the seventh example, andthus do not limit the scope of the present invention. First, as shown inFIG. 42( a), a first stopper film 92 to be used as a stopper during theCMP step later performed and, depending on the necessity, a sacrificelayer for improvement of the coating capability for the low-permittivityfilm are formed on a semiconductor substrate on which the shallow-trenchisolation film 2, MOSFETs 3 and W contact plugs 5 have been formed. Thefirst stopper film 92 should be preferably made of a material assuring aselectivity ratio against the low-permittivity insulating film 7 andsacrifice layer 97 during the CMP step, and examples thereof includeSiN, SiON, and SiCN. The sacrifice layer 97 should preferably be aninsulating film including silicon and oxygen, and the examples thereofinclude SiO₂. More preferably, the sacrifice layer 97 is made of ahydrophilic material in the view point of coating capability improvementin the case of forming the low-permittivity insulating film 7 by acoating technique.

Thereafter, as shown in FIG. 42( b), patterning is performed usingphotoresist 98 for later forming the low-capacitance substrate region.The shape of patterning may be a square lattice arrangement, obliquearrangement, random arrangement or groove lattice, as recited in thefirst embodiment in this text. Moreover, it may be a so-calledhoney-comb structure wherein hexagon openings are arranged to improvethe filling factor.

Thereafter, as shown in FIG. 42( c), the sacrifice layer 97, firststopper insulating film 92, first interlevel dielectric film 4, andshallow-trench element isolation film 2 are etched by plasma-enhancedetching using the photoresist 98 as a mask, to form openings 99 a.Subsequently, as shown in FIG. 43( d), the silicon substrate 1 is etchedby plasma-enhanced etching to form openings 99 b. The peel-off of thephotoresist 98 shown in FIG. 43( c)′, may be performed after the etchingof the silicon substrate.

Thereafter, as shown in FIG. 43( e), a low-permittivity insulating film7 is formed for filling the openings. The materials shown in theembodiments of this text are used for the low-permittivity insulatingfilm 7.

Thereafter, unnecessary low-permittivity insulating film 7 and sacrificelayer 97 are removed by CMP, wherein the first stopper insulating film92 acts as a stopper for the CMP during this CMP, and the structureshown in FIG. 44( f) is formed after the CMP. Subsequently, a secondstopper insulating film 93 is formed (FIG. 44( g)).

Thereafter, as shown in FIG. 44( h), a desired interconnection trenchpattern is formed using photoresist 101, followed by etching the secondinterlevel dielectric film 9 by plasma-enhanced etching, as shown inFIG. 45( i). In this step, the second stopper insulating film 93 acts asan etch stopper and prevents the low-permittivity insulating rods 8 frombeing etched during the etching of the second interlevel dielectric film9. During the etching of the second interlevel dielectric film 9, a hardmask technique using an insulating film formed on the second interleveldielectric film 9 may be used instead of the resist mask, although notdepicted therein.

Thereafter, the second stopper insulating film 93, first stopperinsulating film 92 and low-permittivity insulating rods 8 areconcurrently etched by plasma-enhanced etching using the secondinterlevel dielectric film 9 as a mask. A barrier metal film 102depending on the necessity and a metallic interconnect layer 10 aredeposited on the entire surface including the interconnection trenchformed by the plasma-enhanced etching, and unnecessary metallic filmsare removed by CMP to obtain the structure shown in FIG. 45( k).

The present fabrication method provides a flat surface for the bottom ofthe first metallic interconnects 10, especially if the first metallicinterconnects 10 are formed in the second interlevel dielectric film 9located on the low-capacitance substrate region in the case wheremetallic interconnects including copper as the main component thereofare formed using a damascene technique on the semiconductor substrateincluding therein low-capacitance substrate region. Thus, theperformances, such as stability of the line resistance of the metallicinterconnects 10, reliability of the insulation, which are required ofthe metallic interconnects formed in the semiconductor device can besatisfied.

Tenth Example

Next, referring to FIGS. 46 to 48, a fabrication method for forming thestructure of the eighth embodiment of the present invention will bedescribed in detail. The fabrication method is an example for achievingthe eighth embodiment of the present invention, and thus do not limitthe scope of the present invention. The steps of this example are sameas the steps of the method of the ninth example up to the step shown inFIG. 43( e), and thus the description thereof is omitted for the stepsup to the step of FIG. 43( e) and will be started at FIG. 46( e) whichshows the same structure as FIG. 43( e).

After forming the structure shown in FIG. 46( e), the low-permittivityinsulating film 7 is etched by plasma-enhanced etching to form thelow-permittivity insulator rods 8 (FIG. 46( f)). The etching conditionsshould preferably include the condition for assuring the selectivityratio against the sacrifice layer 97. Subsequently, the cap insulatingfilm 94 is deposited so as to fill the openings on the low-permittivityinsulator rods 8. The cap insulating film 94 should preferably be madeof a material having a higher permittivity and a higher mechanicalstrength, such as in elastic modulus and hardness, than thelow-permittivity insulator rods 8, and thus an insulating materialcapable of being removed together with the sacrifice layer 97 by usingCMP.

Thereafter, the cap insulating film 94 and sacrifice layer 97 areremoved for planarization using CMP. In this step, the first stopperinsulating film acts as a CMP stopper, whereby the structure shown inFIG. 47( h) is formed after the CMP.

Thereafter, as shown in FIG. 47( i), the second stopper insulating film93 and second interlevel dielectric film 9 are deposited, followed byforming a desired interconnection trench pattern by using photoresist101, as shown in FIG. 47( j), and plasma-enhanced etching to obtain thestructure shown in FIG. 48( k). In this step, the second stopperinsulating film 93 acts as an etch stopper and prevents the capinsulating film 94 from being etched during the etching of the secondinterlevel dielectric film 9. For the etching of the second interleveldielectric film 9, a hard mask technique may be used using an insulatingfilm formed on the second interlevel dielectric film 9 in advance,instead of using the resist mask, although not depicted therein.

Thereafter, using the second interlevel dielectric film 9 as a mask, thesecond stopper insulating film 93, first stopper insulating film 92 andcap insulating film 94 are concurrently etched by plasma-enhancedetching (FIG. 48( l)). Moreover, a barrier metal layer 102 depending onthe necessity, and metallic interconnects 101 are deposited, and thenunnecessary metallic films are removed by CMP to obtain the structure ofFIG. 48( m).

The fabrication method provides a flat surface for the bottom of thefirst metallic interconnects 10, if the first metallic interconnects 10formed in the second interlevel dielectric film 9 located on thelow-capacitance substrate region in the case where metallicinterconnects including copper as the main component thereof are formedusing a damascene technique on the semiconductor substrate includingtherein the low-capacitance substrate region. Thus the performances,such as stability of the line resistance of the metallic interconnects10 and reliability of insulation, which are requested of the metallicinterconnects formed in the semiconductor device can be satisfied.

Eleventh Example

Next, referring to FIG. 49, a fabrication method for forming thestructure of the ninth example of the present invention will bedescribed. The fabrication method is an example for achieving the ninthembodiment of the present invention, and thus does not limit the scopeof the present invention. The steps of this example are same as thesteps of the method of the ninth example for the steps up to the stepshown in FIG. 43( e), and thus the description thereof is omitted forthe steps up to the step of FIG. 43( e) and will be started at FIG. 49(e) which shows the same structure as FIG. 43( e).

After forming the structure shown in FIG. 49( e), unnecessarylow-permittivity insulating film 7 is removed by plasma-enhanced etchingto form the low-permittivity insulator rods 8 (FIG. 49( f)). Formanufacturing the structure of the ninth embodiment of the presentinvention, it is necessary that the topmost position of thelow-permittivity insulator rods 8 be located lower than the topmostposition of the W contact plugs 5 after the plasma-enhanced etching. Thecap insulating film 94 is later formed on top of the low-permittivityinsulator rods 8 by using this step difference.

Thereafter, as shown in FIG. 49( g), an insulator cap 94 is deposited.The material for the insulator cap 94 should preferably be made of amaterial having a higher mechanical strength than the low-permittivityinsulating film configuring the low-permittivity insulator rods 8 and aresistance against the sputtering for a metal containing titanium,aluminum etc. and etching plasma for the metallic interconnects.

Thereafter, unnecessary cap insulating film 94 and sacrifice layer 97are removed using CMP. The first stopper insulating film 92 acts as aCMP stopper, whereby the sectional structure shown in FIG. 50( h) isformed after the CMP. It is sufficient that the CMP condition be setsuch that the cap insulating film 94 and sacrifice layer 97 can beremoved and a selectivity ratio against the first stopper insulatingfilm 92 is assured.

After forming the structure shown in FIG. 50(I), the first stopperinsulating film 92 is removed using plasma-enhanced etching. It issufficient that the conditions of the plasma-enhanced etching be setsuch that the top surface of the W contact plugs is exposed. If theselectivity ratio is secured between the first stopper insulating film92 and the cap insulating film 94, then the shape of FIG. 50( i) isobtained, whereas if the selectivity ratio is not secured and theetching proceeds concurrently, then the shape of FIG. 50( i)′ isobtained. In view of the bottom flatness of the interconnects, the shapeof FIG. 50( i)′ is more preferable.

After the steps as described above, the multi-layered interconnectionstructure is formed according to the manufacturing process for thealuminum interconnects generally used, to thereby obtain the structureshown in FIGS. 51( j) and 51(j)′ (wherein the detail of the steps formanufacturing the aluminum interconnects is not depicted).

1. A semiconductor device comprising a semiconductor substrate, atransistor formed on a surface area of said semiconductor substrate, anda multi-layered interconnection structure including a plurality ofinterlevel dielectric films and a plurality of interconnect layersoverlying said transistor, wherein a high-permeability region isprovided in an interlevel dielectric film, wherein: saidhigh-permeability region includes therein a plurality ofhigh-permeability magnetic rods including a high-permeability materialembedded in respective film openings, said film openings having anaspect ratio (depth/diameter or a side) of 1 or above and penetrating atleast one of said interlevel dielectric films to reach another of saidinterlevel dielectric films, said high-permeability material is acomposite material including a low-permittivity insulating material anda high-permeability magnetic material including an electric conductivityor an insulating property.
 2. The semiconductor device according toclaim 1, wherein said low-permittivity insulating material is a porousinsulating material.
 3. A semiconductor device comprising asemiconductor substrate having therein a low-capacitance substrateregion, a transistor formed on a surface area of said semiconductorsubstrate, and a multi-layered interconnection structure including aplurality of interlevel dielectric films and a plurality of interconnectlayers overlying said transistor, wherein: a plurality of substrateopenings are formed in said low-capacitance substrate region,penetrating at least an undermost one of said interlevel dielectricfilms to reach an internal of said semiconductor substrate, an on-chipantenna interconnect is formed on said low-capacitance substrate regionand is configured by interconnect layers embedded in slit-like openingswhich are formed to penetrate a plurality of said interlevel dielectricfilms.
 4. A semiconductor device comprising a semiconductor substratehaving therein a low-capacitance substrate region, a transistor formedon a surface area of said semiconductor substrate, and a multi-layeredinterconnection structure including a plurality of interlevel dielectricfilms and a plurality of interconnect layers overlying said transistor,wherein: a plurality of substrate openings are formed in saidlow-capacitance substrate region, penetrating at least an undermost oneof said interlevel dielectric films to reach an internal of saidsemiconductor substrate, an on-chip antenna interconnect is formed onsaid low-capacitance substrate region in a peripheral area of asemiconductor chip, and a grounded shield interconnect is formed insidesaid on-chip antenna interconnect.
 5. The semiconductor device accordingto claim 4, wherein said shield interconnect is configured byinterconnect layers embedded in slit-like openings formed to penetrate aplurality of said interlevel dielectric films.